52 lines
1.5 KiB
VimL
52 lines
1.5 KiB
VimL
" Author: Masahiro H https://github.com/mshr-h
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" Description: iverilog for verilog files
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if exists('g:loaded_ale_linters_verilog_iverilog')
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finish
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endif
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let g:loaded_ale_linters_verilog_iverilog = 1
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function! ale_linters#verilog#iverilog#Handle(buffer, lines)
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" Look for lines like the following.
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"
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" tb_me_top.v:37: warning: Instantiating module me_top with dangling input port 1 (rst_n) floating.
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" tb_me_top.v:17: syntax error
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" memory_single_port.v:2: syntax error
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" tb_me_top.v:17: error: Invalid module instantiation
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let l:pattern = '^[^:]\+:\(\d\+\): \(warning\|error\|syntax error\)\(: \(.\+\)\)\?'
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let l:output = []
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for l:line in a:lines
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let l:match = matchlist(l:line, l:pattern)
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if len(l:match) == 0
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continue
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endif
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let l:line = l:match[1] + 0
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let l:type = l:match[2] ==# 'warning' ? 'W' : 'E'
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let l:text = l:match[2] ==# 'syntax error' ? 'syntax error' : l:match[4]
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call add(l:output, {
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\ 'bufnr': a:buffer,
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\ 'lnum': l:line,
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\ 'vcol': 0,
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\ 'col': 1,
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\ 'text': l:text,
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\ 'type': l:type,
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\ 'nr': -1,
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\})
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endfor
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return l:output
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endfunction
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call ale#linter#Define('verilog', {
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\ 'name': 'iverilog',
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\ 'output_stream': 'stderr',
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\ 'executable': 'iverilog',
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\ 'command': g:ale#util#stdin_wrapper . ' .v iverilog -t null -Wall',
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\ 'callback': 'ale_linters#verilog#iverilog#Handle',
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\})
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