Add verilator for verilog

2016-10-08 21:38:31 +09:00
parent edc5cedd8c
commit e59264023a
3 changed files with 52 additions and 2 deletions
--- a/doc/ale.txt
+++ b/doc/ale.txt
@@ -61,7 +61,7 @@ The following languages and tools are supported.
 * SCSS: 'sasslint', 'scsslint'
 * Scala: 'scalac'
 * TypeScript: 'tslint'
-* Verilog: 'iverilog'
+* Verilog: 'iverilog', 'verilator'
 * Vim: 'vint'
 * YAML: 'yamllint'