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Add verilator for verilog

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mshr-h
2016-10-08 21:38:31 +09:00
parent edc5cedd8c
commit e59264023a
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@@ -47,7 +47,7 @@ name. That seems to be the fairest way to arrange this table.
| SCSS | [sass-lint](https://www.npmjs.com/package/sass-lint), [scss-lint](https://github.com/brigade/scss-lint) |
| Scala | [scalac](http://scala-lang.org) |
| TypeScript | [tslint](https://github.com/palantir/tslint) |
| Verilog | [iverilog](https://github.com/steveicarus/iverilog) |
| Verilog | [iverilog](https://github.com/steveicarus/iverilog), [verilator](http://www.veripool.org/projects/verilator/wiki/Intro) |
| Vim | [vint](https://github.com/Kuniwak/vint) |
| YAML | [yamllint](https://yamllint.readthedocs.io/) |