Match both error and syntax error in verilog

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Bjorn Neergaard 2016-10-11 12:08:31 -05:00
parent 572c877a69
commit 93cd44e2ec
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@ -25,7 +25,7 @@ function! ale_linters#verilog#iverilog#Handle(buffer, lines)
endif
let l:line = l:match[1] + 0
let l:type = l:match[2] ==# 'error' ? 'E' : 'W'
let l:type = l:match[2] =~# 'error' ? 'E' : 'W'
let l:text = l:match[2] ==# 'syntax error' ? 'syntax error' : l:match[4]
call add(l:output, {